As the speed of signals flowing between a packaged device and a printed circuit board to which it is coupled increases, the need to reduce signal discontinuities caused by changes in impedance between the package and the printed circuit board increases. Minimization of discontinuities allows for high bandwidth and high signal quality. Discontinuities include changes in impedance of a transmission line and/or signal reference of a transmission line over which a signal is traveling.
To ensure proper operation between various chips on a printed circuit board, manufacturers specify the characteristic impedance of signal paths running on or within the printed circuit board. Manufacturers also provide a tolerance for the characteristic impedance of these traces. For example, the characteristic impedance of system bus trace may be specified as being 50 Ohms±15%.
Various design guidelines have been developed to maintain trace impedance within specified tolerance on the printed circuit board. These guidelines are, by their nature, restrictive. One such guideline is the “Intel® Pentium® 4 Processor in 478-pin Package and Intel® 845 Chipset Platform Design Guide,” which may be found at the Intel® Developer Web Site at http://developer.intel.com/design/chipsets/designex/29835401.pdf. The Intel® guideline describes a four layer printed circuit board design that includes two external signal layers (one each on a primary and secondary side, respectively) and two internal planes. One of the internal planes is usually a power plane (e.g., VCC) and the other internal plane is usually a continuous ground plane (e.g., VSS). The four planes lie parallel to each other; each separated from the other by a layer of dielectric. The guideline requires that the processor side bus signals on the four-layer printed circuit board maintain ground (e.g., VSS) as a reference plane. See Section 4.1, Processor System Bus Design Guidelines. By this constraint, the guideline seeks to ensure a continuous return path for an electrical signal traveling on the system bus both within the package and the printed circuit board. The return path is the route current takes to return to its source, otherwise known as the image current. It may take a path through, for example, ground planes, power planes, other signals, integrated circuits, passive components such as resistors or capacitors, and/or vias. By requiring system bus signals to reference ground, the design guideline avoids discontinuities in characteristic impedance of a trace by clearly specifying a known and continuous reference.
A problem, however, is imposed on a printed circuit board layout when signal path routing is restricted to reference only the ground plane. This means, in a four layer printed circuit board, that the signal path layer can only be routed on one side of the printed circuit board, for example, the primary side, because, usually, only the primary side lies adjacent to the internal plane that has been designated as a ground plane. In that situation, signal paths cannot be placed on the secondary side because the secondary side's conductive layer lies adjacent to, and thus is referenced to, the internal plane that had been designated as the power plane layer. This constraint eliminates an entire conductive plane that could be used for signal path routing. Furthermore, this constraint on the layout of the printed circuit board results in escape and routing issues from a ball grid array (“BGA”) component, or a pin grid array (“PGA”) component, coupled to the printed circuit board within the BGA (or PGA) to printed circuit board interface area. These issues become increasingly significant as the density of microelectronics on the printed circuit board increase, and as the speed of the signals on the printed circuit board increase.
The difficulties imposed by typical guideline constraints, such as that mentioned above, have been addressed in the past by modifications to the printed circuit board. For example, in the four layer printed circuit board, rather than providing a unitary plane, the internal power plane layer may be populated by contiguous yet electrically isolated islands (frequently referred to as power plane flood areas); some of the islands may maintain their designation as the power plane layer while the remainder of the islands may be re-designated as ground plane areas. Traces on the component attachment layer may then be routed above the ground plane islands and are thus referenced to the ground plane. This solution is disfavored as segmentation of the power plane leads to a host of other problems. For example, the creation of ground plane islands on the power plane will result in significant challenges to delivering power on the printed circuit board from voltage regulator modules to respective components due to trace congestion, especially on areas close to the components.
Another modification may be to increase the number of layers in the printed circuit board, for example, from four to six layers. This is typically accomplished by designating the two outer layers as signal layers. Each outer signal layer references an adjacent internal ground plane. Additional internal power planes lie adjacent to the internal ground planes; one outer layer and one power plane each sandwich one ground plane. The six planes lie parallel to each other and are separated from one another by dielectric layers. While this solution can produce a very robust design, a six-layer printed circuit board tends to be prohibitively expensive to such industries as, for example, the high volume cost sensitive personal computer industry.
Other modifications to the printed circuit board may include applying finer printed circuit board design rules to provide for reduced diameter pads or reduced spacing between traces routed to the BGA or PGA. This has the effect of increasing the density of signal paths present on the signal path routing layer. Increased trace density, however, comes at the expense of increased cross-talk between traces. Another modification to the printed circuit board might be to increase the spacing between the lands that accept the BGA or PGA. This may provide for more traces to be interspersed between the BGA or PGA connectors, but it also requires a corresponding increase in package body size. While each of these modifications is applied to provide escape routing for all signal paths, they each result in increased overall system cost and complexity. Furthermore, they are all addressed toward changes in printed circuit board design and do not provide for improvements to package design.